// 2T2R // Date: 2009/01/09
0x01c 0x07000000 //for B-cut power on initinal RF
//=======================
// PAGE_8 ( FPGA_PHY0 )
//=======================
0x800 0x00040000 //by JY, disable OFDM and CCK when initial //0x03040000 //0x00050000 (enable watch_dog)
0x804 0x00008003 //When should SI_RW be asserted? 080825
0x808 0x0000fc00 //0x00000000 (set value for PSD module)
0x80c 0x0000000A //080817 JH set to OFDM mode //(reduce TX power)0x00000007
//0x810 0x10001022 //0x801010ff(delay PA starting time at TX)0x202020bb //(increase MACTXen to TXpe duration)0x20202088 (after 061208) //0x08000068
0x810 0x10005088 //0x100010aa Fixed by Wilson 081215 //0x10001044 // 44 has IOT in B/G mode
0x814 0x020c3d10 //0x002118c0 //(ccamask_ofdm=5.2us, ccamask_intf=2us)0x0018dad0 //0x000018c0 (before 1213) //0x00000000 //0x08000068
0x818 0x00200185 //0x002003c5 // ECO test ok by Jerry 0x000003c5//0x00000000 //0x08000068
0x81c 0x00000000 //0x08000068
//0x820 0x01000100 //Use PI interface, by YTChen 1201 0x01000000 //0x00000000 is used for 0222D FPGA with SI interface. 080825
0x820 0x01000000 // Use SI interface
0x824 0x00390004 //(enable cck highpower)
//0x828 0x01000100 //Use PI interface, by YTChen 0x01000000 //0x00000000 is used for 0222D FPGA with SI interface. 080825
0x828 0x01000000
0x82c 0x00390004 // by JY 081219 // for 2T2R by YN 081130//0x00390004 //(enable cck highpower)
0x830 0x00000004
0x834 0x00690200 //0x00600000 (enable cck highpower)
0x838 0x00000004
0x83c 0x00690200 //0x00600000 (enable cck highpower)
0x840 0x00010000 // by JY 081219  //0x00000000
0x844 0x00010000 // by JY 081219  //0x00000000
0x848 0x00000000
0x84c 0x00000000
0x850 0x00000000
0x854 0x00000000
0x858 0x48484848 //0x65A965A9 // Fixed by YN 081215 //(TRSW&TRSWB polarity )0xa965a965
0x85c 0x65A965A9 //(TRSW&TRSWB polarity )0xa965a965
0x860 0x0f7f0130 //(1T2R, RF-A/B off)(RFENV->SW control)0x001f0000 //only 3-wire and RF_ENV output enable//0xffff0130
0x864 0x0f7f0130 // by JY 081219 //for 2T2R, open AntB, 0x0f7f0130 //(TRSW&TRSWB output enable for Path-B)0x001f0010 //(RFENV->SW control for Path-B)0x001f0000 //only 3-wire and RF_ENV output enable//0xffff0130
0x868 0x0f7f0130 //(RFENV->SW control)0x001f0000 //only 3-wire and RF_ENV output enable//0xffff0130
0x86c 0x0f7f0130 //(TRSW&TRSWB output enable for Path-D)0x001f0010 //(RFENV->SW control for Path-D)0x001f0000 //only 3-wire and RF_ENV output enable//0xffff0130
0x870 0x03000700 //(TRSW&TRSWB hardware control for Path-B)0x0f700f70 //(RFENV->SW control for Path-B)0x0f600f60 //TRSW, PAPE & AntSW software ontrol for Z4
0x874 0x03000300 //(TRSW&TRSWB hardware control for Path-D)0x0f700f70 //(RFENV->SW control for Path-D)0x0f600f60 //TRSW, PAPE & AntSW software ontrol for Z4
0x878 0x00020002 //0x00000000 // Fixed by YN 081215 for 2T //
0x87c 0x004f0201 //RTL8712-8192S ASIC-TEST MODE control, 080822
0x880 0xa8300ac1 //Change AFE 080827 //0xa9324ac1 //RTL8712-8192S ASIC-AFE control, 080822
0x884 0x00000058 //0x00000018 // 20/40M mode CCK clk = 44/88 initial at 40M mode //RTL8712-8192S ASIC-AFE control, 080822
0x888 0x00000008 //RTL8712-8192S ASIC-AFE control, 080822
0x88c 0x00000004 //RTL8712-8192S ASIC-MAC control, 080822
0x890 0x00000000
0x894 0xfffffffe //(add CCX counter)0x00000000
0x898 0x40302010 //(add nhm TH)0x00000000
0x89c 0x00706050 //(add nhm TH)0x00000000
0x8b0 0x00000000
0x8e0 0x00000000
0x8e4 0x00000000
//
//=======================
// PAGE_E, 070817: JH add page E for TXAGC codeword setting
//=======================
// For non-PG power index
0xe00 0x30333333 //0x03030303 is used for 0222D FPGA, 080825 // for 18M,12M,09M,06M
0xe04 0x2a2d2e2f //0x03030303 is used for 0222D FPGA, 080825 // for 54M,48M,36M,24M
0xe08 0x00003232 //0x03030303 is used for 0222D FPGA, 080825 // for CCK
//0xE0c 0x00000000
0xe10 0x30333333 //0x03030303 is used for 0222D FPGA, 080825 // for M0~M3
0xe14 0x2a2d2e2f //0x03030303 is used for 0222D FPGA, 080825 // for M4~M7
0xe18 0x30333333 //0x03030303 is used for 0222D FPGA, 080825 // for M8~M11
0xe1c 0x2a2d2e2f //0x03030303 is used for 0222D FPGA, 080825 // for M12~M15
// IQ calibration setting , added at 08/01/11
0xe30 0x01007c00
0xe34 0x01004800
0xe38 0x1000dc1f
0xe3C 0x10008c1f
0xe40 0x021400a0
0xe44 0x281600a0
0xe48 0xf8000001
0xe4C 0x00002910
0xe50 0x01007c00
0xe54 0x01004800
0xe58 0x1000dc1f
0xe5C 0x10008c1f
0xe60 0x021400a0
0xe64 0x281600a0
0xe6C 0x00002910
// Analog Setting
// Change by Wilson 2008/11/04, 2008/11/13 fixed
0xe70 0x31ed92fb // RX_WAIT_CCA, turn off PA//0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V // RTL8712-8192S ASIC-analog power saving control, 080822
0xe74 0x361536fb // TX_CCK_RFON //0x360936fb//0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xe78 0x361536fb // TX_CCK_BBON //0x360936fb//0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xe7c 0x361536fb // TX_OFDM_RFON //0x360936fb//0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xe80 0x361536fb // TX_OFDM_BBON //0x360936fb//0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xe84 0x000d92fb // TX_TO_RX turn off //0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xe88 0x000d92fb // TX_TO_TX turn off //0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xe8c 0x31ed92fb // RX_CCK, turn off DA //0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xed0 0x31ed92fb // RX_OFDM, turn off DA//0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xed4 0x31ed92fb // RX_WAIT_RIFS, turn off DA//0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xed8 0x000d92fb // RX_TO_RX, turn off all//0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xedc 0x000d92fb // NAV mode, turn off all//0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xee0 0x000d92fb // Sleep mode, turn off all//0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V// Change AFE 080827 //0x000d92f3
0xee4 0x015e5448
0xee8 0x21555448 // Willis fixed
//=======================
// PAGE_9 ( FPGA_PHY1 )
//=======================
0x900 0x00000000
0x904 0x00000023
0x908 0x00000000
0x90c 0x03321333 //for 1SS2TX //0x01121313 (for next version after 1031, add non_ht_s1, LBK needs change)
//
//=======================
// PAGE_A ( CCK_PHY0 )
//=======================
0xa00 0x00d047c8
0xa04 0x80ff0008 //0xc1ff0008 // Fixed by YN 081215
0xa08 0x8ccd8300 //0x8c838300 Fixed by Luke 090109
0xa0c 0x2e62120f //by YN in 081130//0x2e6c120f
0xa10 0x9500bb78 //0x95009b78 // Fixed by YN 081215 
0xa14 0x11144028
0xa18 0x00881117
0xa1c 0x89140f00
0xa20 0x1a1b0000 // by YN 081225 //0x25260010
0xa24 0x090e1317 // by YN 081225 //0x0d141b21
0xa28 0x00000204 // by YN 081225 //0x00000306
0xa2c 0x10d30000
//
//=======================
// PAGE_C ( OFDM_PHY0 )
//=======================
0xc00 0x40071d40 //0x00071d40 // by Dz 081215//0x00000040 //bit30 set tssi report=1
0xc04 0x00a05633 //fixed_12/04 by Jenyu, AD5 sampling clock = 8M // 0x00a05411 // JH adds frame_TH2_GI2 to deal with CDD-400 //0xc04 0x00005433 //0x00000033 // 070817 JH add default value for RegC04[7:4]=3, This register world work for RTL8192 and later projects
0xc08 0x000000e4
0xc0c 0x6c6c6c6c //0x14141414(unsign, offset is defined as positive)
0xc10 0x08800000 //0x00000000(enable DC NF filter)
0xc14 0x40000100
0xc18 0x08000000
0xc1c 0x40000100
0xc20 0x08000000
0xc24 0x40000100
0xc28 0x08000000
0xc2c 0x40000100
0xc30 0x6de9ac44 //0x8de96C44 //0x6de9cd45 //0x6de98d4b //(tight MF)0x6de98d47 //0x6de9cd49 (version before 0107)
0xc34 0x469652cf // by Dz 081215 //0x469652cd //0x158052cd //0x154052cd(sub=2) //0x144052cd //0x144030d5
0xc38 0x49795994 // by Dz 081215 //0x497f5994 //0x00010a10 //0x00010a13
0xc3c 0x0a979764 // 0x0a97af64 //(modify SGI)0x9e97af64 //(tight DC)0x9e97ab14 //0x9f37ab14
0xc40 0x1f7c403f //0x007c423f(enable notch filter auto selection)
0xc44 0x000100b7 //0x000100c7
0xc48 0xec020000
0xc4c 0x007f037f //0x00000388 //0x00000398 (edcca H-to-L)
0xc50 0x69543420 //0xe954341c //0xe9543420 (initial=-74dBm)//0xeaa03420 //0xe9543420
0xc54 0x433c0094 //0x433c0194 //0x00000194
0xc58 0x69543420 //0xe954341c //0xe9543420 //0xeaa03420 //0xe9543420
0xc5c 0x433c0094 //0x433c0194 //0x00000194
0xc60 0x69543420 //0xe954341c //0xe9543420 //0xeaa03420 //0xe9543420
0xc64 0x433c0094 //0x433c0194 //0x00000194
0xc68 0x69543420 //0xe954341c //0xe9543420 //0xeaa03420 //0xe9543420
0xc6c 0x433c0094 //0x433c0194 //0x00000194
0xc70 0x2c7f000d //0x2c40aaa5 (version before 1025)
0xc74 0x0186155b //0x0186151b //RSSI AGC timing
0xc78 0x0000001f
0xc7c 0x00b91612 //0x00b81612
0xc80 0x40000100
0xc84 0x20f60000 // by Dz 081215 //0x20460000 // Add parameters for CDD=-400 //0x20000000//0x00000000 (set pdth_bw40)
0xc88 0x20000080
0xc8c 0x20200000 // Perform preamble_antenna_weighting by AGC 080825//0x00000000 (before 1221)
0xc90 0x40000100
0xc94 0x00000000
0xc98 0x40000100
0xc9c 0x00000000
0xca0 0x00492492 //-- TX channel emulator --
0xca4 0x00000000
0xca8 0x00000000
0xcac 0x00000000
0xcb0 0x00000000
0xcb4 0x00000000
0xcb8 0x00000000
0xcbc 0x28000000 //0xcbc 0x00492492 JH add r_MRC_byAGC_TH 080612
0xcc0 0x00000000
0xcc4 0x00000000
0xcc8 0x00000000
0xccc 0x00000000
0xcd0 0x00000000
0xcd4 0x00000000
0xcd8 0x64b22427 //0x64b22326 (old) //-- DFS funciton --
0xcdc 0x00766932 //0x00758d63 (old)
0xce0 0x00222222 //new 3-bits RXHP setting
0xce4 0x00000000
0xce8 0x37644302 // JH enable force_indtx_en 080616
0xcec 0x2f97d40c  // JH add tracking mode threshold 080612
//
//=======================
// PAGE_D ( OFDM_PHY1 )
//=======================
0xd00 0x00000750 //(add default ctrl_ch in RF_mode=40M)0x00000380
0xd04 0x00000403 //0x00000003
0xd08 0x0000907f //0x0000003f //0x0000001f (before 1213) //0x000000c7
0xd0c 0x00000001 //0x00000000
0xd10 0xa0633333 //0xa0777777 //0xa0700000(for old s_factor) //0xa0755555 (smaller S_factor)
0xd14 0x33333c63 //0x77773c67 //0x00000067(for old s_factor)
0xd18 0x6a8f5b6b //0x0a8f5b6f(add csi_mask) //0x028f5b6f(for csi_val_gated) //0x020f5b6f (enable antenna weight)
0xd1c 0x00000000
0xd20 0x00000000
0xd24 0x00000000
0xd28 0x00000000
0xd2c 0xcc979975 //0xcc9fd974 //0x0c9fd974(for preset_csi_scheme/smooth) //0x0c9f9974 (for fc=2.4G, but FPGA is downrate by 2/4)
0xd30 0x00000000
0xd34 0x00000000
0xd38 0x00000000
0xd3c 0x00027293 //(reduce TH)0x000272d3 //interference detection disable for sensitivity test
0xd40 0x00000000
0xd44 0x00000000
0xd48 0x00000000
0xd50 0x6437140a //(add initial state of noise generator)0x00000000
0xd54 0x024dbd02 //(add initial state of noise generator)0x00000000
0xd58 0x00000000
0xd5c 0x30032064 //0x2d432064 //(add weighting scheme)0x00832064 //(add antenna weighting TH)0x00032064
0xd60 0x4653de68
0xd64 0x00518a3c
0xd68 0x00002101 // Turn on second time CFO estimation //0x00000186
0xf14 0x00000003 // Only for PMAC mode: debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG
0xf4c 0x00000000 // Only for PMAC mode: Only for ASIC-PMAC
0xf00 0x00000300 // Only for PMAC mode: enable BBRSTB, bcz HSSI use clk_bb
0xff
