//=======================
// PHY related
//=======================
//0x804 0x0000000f 0x2 //When should SI_RW be asserted? 080825
0x824 0x00f0000f 0x100002 //or 0x00090200(enable cck highpower)
0x82c 0x00f0000f 0x300004 //(enable cck highpower)
0x870 0x00000400 0x1 // SW control Ant A PAPE
0x860 0x00000400 0x0 // close Ant A PAPE
0x878 0x000f000f 0x20000 // by YN 1215
// Analog Setting
0xe74 0x0f000000 0x4 // TX_CCK_RFON //0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xe78 0x0f000000 0x4 // TX_CCK_BBON //0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xe7c 0x0f000000 0x4 // TX_OFDM_RFON //0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
0xe80 0x0f000000 0x4 // TX_OFDM_BBON //0x3fed92f3/0x3fe912f3/0x3fe492f3 com mode =0.8V/0.6V/0.4V
//
0x90c 0x0ff000ff 0x2200022 //for 1SS2TX //0x01121313 (for next version after 1031, add non_ht_s1, LBK needs change)
0xc04 0x000000ff 0x22 // JH adds frame_TH2_GI2 to deal with CDD-400 //0xc04 0x00005433 //0x00000033 // 070817 JH add default value for RegC04[7:4]=3, This register world work for RTL8192 and later projects
0xd04 0x0000000f 0x2 //0x00000003
0xa04 0xff000000 0x41 // CCK Tx Rx in Ant B

// MAC
//0x184 0x0f000000 0x100ff0f0 //0x100ff0f5 // B,G,N mode // 0x10000ff5 B,G mode // 0x0000000d B mode // CCK2M not support
//0x1f6 0x0000ffff 0x00007777 // B,G,N mode 1 SS
0x234 0xf8000000 0xa
//0x2c0 0xffffffff 0xd0000000
//0x2c0 0xffffffff 0xe0000000 // Reset RA

0xff